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Freescale Semiconductor Advance Information
MR2A16A/D Rev. 0.1, 7/2004
256K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM
Introduction
The MR2A16A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as 262,144 words of 16 bits. The MR2A16A is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for significant system design flexibility without bus contention. Because the MR2A16A has separate byte-enable controls (LB and UB), individual bytes can be written and read. MRAM is a nonvolatile memory technology that protects data in the event of power loss and does not require periodic refreshing. The MR2A16A is the ideal memory solution for applications that must permanently store and retrieve critical data quickly. The MR2A16A is available in a 400-mil, 44-lead plastic small-outline TSOP type-II package with an industry-standard center power and ground SRAM pinout.
Features * * * * * * * * * Single 3.3-V power supply Commercial temperature range (0C to 70C) Symmetrical high-speed read and write with fast access time (25 ns) Flexible data bus control -- 8 bit or 16 bit access Equal address and chip-enable access times Automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss All inputs and outputs are transistor-transistor logic (TTL) compatible Fully static operation Full nonvolatile operation with 10 years minimum data retention
(c) Freescale Semiconductor, Inc., 2004. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice.
Device Pin Assignment
OUTPUT ENABLE BUFFER
G
UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE
A[17:0] ADDRESS BUFFERS 18
8 10 ROW DECODER COLUMN DECODER SENSE AMPS UPPER BYTE OUTPUT BUFFER LOWER BYTE OUTPUT BUFFER 8 FINAL WRITE DRIVERS UPPER BYTE WRITE DRIVER LOWER BYTE WRITE DRIVER 8
8
E
CHIP ENABLE BUFFER 256K x 16 BIT MEMORY ARRAY
16
8
8
W
WRITE ENABLE BUFFER
8
DQU[15:8]
16
8
UB LB
BYTE ENABLE BUFFER LB
UB
UPPER BYTE WRITE ENABLE LOWER BYTE WRITE ENABLE
8
DQL[7:0]
Figure 1. Block Diagram
Device Pin Assignment
A16 A17 A10 A11 A12 E DQL0 DQL1 DQL2 DQL3 VDD VSS DQL4 DQL5 DQL6 DQL7 W A0 A1 A2 A3 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A15 A14 A13 G UB LB DQU15 DQU14 DQU13 DQU12 VSS VDD DQU11 DQU10 DQU9 DQU8 NC A9 A8 A7 A6 A5
Table 1. Pin Functions
Signal Name A[17:0] E W G UB LB DQL[7:0] DQU[15:8] VDD VSS NC Function Address input Chip enable Write enable Output enable Upper byte select Lower byte select Data I/O, lower byte Data I/O, upper byte +3.3-V power supply Ground Do not connect this pin
Figure 2. MR2A16A in 44-Pin TSOP Type II Package
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Electrical Specifications
Table 2. Operating Modes
E H L L L L L L L L G X H X L L L X X X W X H X H H H L L L LB X X H L H L L H L UB X X H H L L H L L Mode Not selected Output disabled Output disabled Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write VDD Current ISB1, ISB2 IDDA IDDA IDDA IDDA IDDA IDDA IDDA IDDA DQL[7:0] Hi-Z Hi-Z Hi-Z DOut Hi-Z DOut DIn Hi-Z DIn DQU[15:8] Hi-Z Hi-Z Hi-Z Hi-Z DOut DOut Hi-Z DIn DIn
NOTES: 1. H = high, L = low, X = don't care 2. Hi-Z = high impedance
Electrical Specifications
Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Table 3. Absolute Maximum Ratings
Parameter Supply voltage Voltage on any pin Output current per pin Package power dissipation Temperature under bias Storage temperature Lead temperature during solder (3 minute max) Maximum magnetic field at package surface Symbol VDD VIn IOut PD TBias Tstg TLead Hmax Value -0.5 to 4.6 -0.5 to VDD + 0.5 20 TBD -10 to 85 -55 to 150 235 20 Unit V V mA W C C C oe
NOTES: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability depends on package characteristics and use environment. MR2A16A/D, Rev. 0.1 Freescale Semiconductor
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Electrical Specifications
Table 4. Operating Conditions
Parameter Power supply voltage Write inhibit voltage Input high voltage Input low voltage Operating temperature NOTES: Symbol VDD VWI VIH VIL TA Min 3.0
(1)
Typ 3.3 2.7 -- --
Max 3.6 3.0
(1)
Unit V V V V C
2.5 2.2 -0.5 0
(3)
VDD + 0.3(2) 0.8 70
1. After power up or if VDD falls below V WI, a waiting period of 1 s must be observed. Memory is designed to prevent writing for all input pin conditions if VDD falls below minimum VWI. 2. VIH (max) = V DD + 0.3 Vdc; VIH (max) = VDD + 2.0 Vac (pulse width 10 ns) for I 20.0 mA. 3. VIL (min) = -0.5 Vdc; VIL (min) = -2.0 Vac (pulse width 10 ns) for I 20.0 mA.
Direct Current (dc) Table 5. dc Characteristics
Parameter Input leakage current Output leakage current Output low voltage (IOL = +4 mA) (IOL = +100 A) Output high voltage (IOH = -4 mA) (IOH = -100 mA) Symbol Ilkg(I) Ilkg(O) VOL Min -- -- -- Typ -- -- -- Max 1 1 0.4 VSS + 0.2 -- Unit A A V
VOH
2.4 VDD - 0.2
--
V
Table 6. Power Supply Characteristics
Parameter ac active supply current -- Read Modes (IOut = 0 mA, VDD = max) Timing Set 20 25 35 20 ac active supply current -- Write Modes (VDD = max) ac standby current (VDD = max, E = VIH) (no other restrictions on other inputs) CMOS standby current (E VDD - 0.2 V and VIn VSS + 0.2 V or VDD - 0.2 V) (VDD = max, f = 0 MHz) 25 35 20 25 35 Symbol IDDR IDDR IDDR IDDW IDDW IDDW ISB1 ISB1 ISB1 ISB2 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit mA mA mA mA mA mA mA mA mA
TBD
TBD
mA
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Electrical Specifications
Table 7. Capacitance
Parameter Address input capacitance Control input capacitance Input/Output capacitance Symbol CIn CIn CI/O Typ -- -- -- Max 6 6 8 Unit pF pF pF
NOTES: 1. (f = 1.0 MHz, dV = 3.0 V, TA = 25C, periodically sampled rather than 100% tested)
Table 8. ac Measurement Conditions
Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Value 1.5 V 1.5 V 0 or 3.0 V 2 ns See Figure 3A See Figure 3B
+3.3 V ZD = 50 OUTPUT RL = 50 VL = 1.5 V OUTPUT 600 5 pF 725
A
B
Figure 3. Output Load for ac Test
MR2A16A/D, Rev. 0.1 Freescale Semiconductor
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Timing Specifications
Timing Specifications
Read Mode Table 9. Read Cycle Timing (See Notes 1 and 2)
Timing Set Parameter Read cycle time Address access time Enable access time Output enable access time Byte enable access time Output hold from address change Enable low to output active Output enable low to output active Byte enable low to output active Enable high to output Hi-Z Output enable high to output Hi-Z Byte high to output Hi-Z Symbol Min tAVAV tAVQV tELQV tGLQV tBLQV tAXQX tELQX tGLQX tBLQX tEHQZ tGHQZ tBHQZ 20 -- -- -- -- 3 3 0 0 0 0 0 20 Max -- 20 20 10 10 -- -- -- -- 10 6 6 Min 25 -- -- -- -- 3 3 0 0 0 0 0 25 Max -- 25 25 11 11 -- -- -- -- 11 7 7 Min 35 -- -- -- -- 3 3 0 0 0 0 0 35 Max -- 35 35 15 15 -- -- -- -- 15 10 10 ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 3 Unit Notes
NOTES: 1. W is high for read cycle. 2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. Addresses valid before or at the same time E goes low. 4. This parameter is sampled and not 100% tested. 5. Transition is measured 200 mV from steady-state voltage.
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Timing Specifications
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
NOTES: 1. Device is continuously selected (E VIL, G VIL).
Figure 4. Read Cycle 1
tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX LB, UB (BYTE ENABLE) tBLQV tBLQX Q (DATA OUT) DATA VALID tBHQZ tGHQZ tEHQZ
Figure 5. Read Cycle 2
MR2A16A/D, Rev. 0.1 Freescale Semiconductor
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Timing Specifications
Write Mode Table 10. Write Cycle Timing 1 (W Controlled; See Notes 1, 2, 3, and 4)
Timing Set Parameter Write cycle time Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Write pulse width (G high) Write pulse width (G low) Data valid to end of write Data hold time Write low to data Hi-Z Write high to output active Write recovery time Symbol Min tAVAV tAVWL tAVWH tAVWH tWLWH tWLEH tWLWH tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX 20 0 12 15 8 8 5 0 0 3 8 20 Max -- -- -- -- -- -- -- -- 7 -- -- Min 25 0 15 17 10 10 6 0 0 3 10 25 Max -- -- -- -- -- -- -- -- 9 -- -- Min 35 0 18 20 15 15 10 0 0 3 12 35 Max -- -- -- -- -- -- -- -- 12 -- -- ns ns ns ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 8 Unit Notes
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4. After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. This parameter is sampled and not 100% tested. 6. Transition is measured 200 mV from steady-state voltage. 7. At any given voltage or temperature, tWLQZ max < tWHQX min. 8. All write cycle timings are referenced from the last valid address to the first transition address.
MR2A16A/D, Rev. 0.1
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Timing Specifications
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLEH tWLWH tAVWL tWHAX
W (WRITE ENABLE)
LB, UB (BYTE ENABLE) tDVWH D (DATA IN) tWLQZ Q (DATA OUT) Hi-Z Hi-Z tWHQX DATA VALID tWHDX
Figure 6. Write Cycle 1 (W Controlled)
MR2A16A/D, Rev. 0.1 Freescale Semiconductor
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Timing Specifications
Table 11. Write Cycle Timing 2 (E Controlled; See Notes 1,2,3, and 4)
Timing Set Parameter Write cycle time Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Enable to end of write (G high) Enable to end of write (G low) Data valid to end of write Data hold time Write recovery time Symbol Min tAVAV tAVEL tAVEH tAVEH tELEH tELWH tELEH tELWH tDVEH tEHDX tEHAX 20 0 12 15 8 8 5 0 8 20 Max -- -- -- -- -- -- -- -- -- Min 25 0 15 17 10 10 6 0 10 25 Max -- -- -- -- -- -- -- -- -- Min 35 0 18 20 15 15 10 0 12 35 Max -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns 5, 6 7 Unit Notes
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4. After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. 6. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. 7. All write cycle timings are referenced from the last valid address to the first transition address.
MR2A16A/D, Rev. 0.1
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Freescale Semiconductor
Timing Specifications
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tELWH tEHAX
LB, UB (BYTE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX
Q (DATA OUT)
Hi-Z
Figure 7. Write Cycle 2 (E Controlled)
MR2A16A/D, Rev. 0.1 Freescale Semiconductor
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Timing Specifications
Table 12. Write Cycle Timing 3 (LB/UB Controlled; See Notes 1, 2, 3, 4, and 5)
Timing Set Parameter Write cycle time Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Byte pulse width (G high) Byte pulse width (G low) Data valid to end of write Data hold time Write recovery time Symbol Min tAVAV tAVBL tAVBH tAVBH tBLEH tBLWH tBLEH tBLWH tDVBH tBHDX tBHAX 20 0 12 15 8 8 5 0 8 20 Max -- -- -- -- -- -- -- -- -- Min 25 0 15 17 10 10 6 0 10 25 Max -- -- -- -- -- -- -- -- -- Min 35 0 18 20 15 15 10 0 12 35 Max -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns 6 Unit Notes
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4. After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. 6. All write cycle timings are referenced from the last valid address to the first transition address.
MR2A16A/D, Rev. 0.1
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Timing Specifications
tAVAV A (ADDRESS) tAVBH E (CHIP ENABLE) tAVBL tBLEH tBLWH tBHAX
LB, UB (BYTE ENABLE) tBHDX W (WRITE ENABLE) tDVBH D (DATA IN) DATA VALID
Q (DATA OUT)
Hi-Z
Hi-Z
Figure 8. Write Cycle 3 (LB/UB Controlled)
MR2A16A/D, Rev. 0.1 Freescale Semiconductor
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Ordering Information
Ordering Information
(Order by Full Part Number) MR Freescale MRAM Memory Prefix Density Code (2 = 4 Mb, 4 = 16 Mb) Memory Type (A = Asynch, S = Sync) 2 A 16 A TS 25 C Operating Temperature Range (C = 0 C to 70 C) Timing Set Package Type (TS = TSOP) Revision (A = rev 1) I/O Configuration (08 = 8 bits, 16 = 16 bits)
Commercial Device Numbers -- MR2A16ATS25C MR2A16ATS35C
TS Package (44-Lead, TSOP Type II, Case 924A-02)
B
44 23
VIEW D 0.15 0.05
10.29 10.03 3 EE
0.60 0.40 5_ 0_ VIEW D ROTATED 90 _ CLOCKWISE
1
22
18.54 18.28 3
A
1.05 0.95 1.20 MAX
22X
11.96 11.56 0.2 M C B
44X
0.1 C
SEATING PLANE 4X
0.8 /2
42X
0.8
C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSIONS DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.15 PER SIDE. 4. DIMENSIONS DO NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58.
Notes
MR2A16A/D, Rev. 0.1
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EEEEE EEEEE EEEEE
0.45 0.30
M
0.21 0.12
0.2
CA
4
SECTION E-E
40 PLACES
Freescale Semiconductor
Notes
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MR2A16A/D, Rev. 0.1 Freescale Semiconductor
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MR2A16A/D
Rev. 0.1, 7/2004

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